SN54ALS374A Datasheet | Texas Instruments

description These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. SN54ALS374A, SN54AS374 . . . J PACKAGE SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54ALS374A, SN54AS374 . . . FK PACKAGE (TOP VIEW) 1D 1Q OE VCC 8Q On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup ponents. 4Q GND CLK 5Q 5D 3 2 1 20 19 2D 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L↑H L↑L L H or L X HXX Q0 Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas...