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SN54BCT646 Datasheet Preview

SN54BCT646 Datasheet

Octal Bus Transceivers

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D State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
D Bus Transceivers/ Registers
D Independent Registers and Enables for
A and B Buses
SN54BCT646 . . . JT OR W PACKAGE
SN74BCT646 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037D − AUGUST 1989 − REVISED MAY 2004
D Multiplexed Real-Time and Stored Data
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54BCT646 . . . FK PACKAGE
(TOP VIEW)
CLKAB 1
SAB 2
DIR 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 VCC
23 CLKBA
22 SBA
21 OE
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
4 3 2 1 28 27 26
A1 5
25 OE
A2 6
24 B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6
1112
13
14
15
16
17
19
18
B5
description/ordering information
NC − No internal connection
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − NT
Tube
SN74BCT646NT
SN74BCT646NT
0°C to 70°C
SOIC − DW
Tube
Tape and reel
SN74BCT646DW
SN74BCT646DWR
BCT646
CDIP − JT
Tube
SNJ54BCT646JT
SNJ54BCT646JT
−55°C to 125°C CFP − W
Tube
SNJ54BCT646W
SNJ54BCT646W
LCCC − FK
Tube
SNJ54BCT646FK
SNJ54BCT646FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1




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SN54BCT646 Datasheet Preview

SN54BCT646 Datasheet

Octal Bus Transceivers

No Preview Available !

SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037D − AUGUST 1989 − REVISED MAY 2004
description/ordering information(continued)
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Part Number SN54BCT646
Description Octal Bus Transceivers
Maker etcTI
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