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SN54HC112 - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

Datasheet Summary

Description

The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

Features

  • Wide operating voltage range of 2 V to 6 V.
  • Outputs can drive up to 10 LSTTL loads.
  • Low power consumption, 40-μA max ICC.
  • Typical tpd = 13 ns.
  • ±4-mA output drive at 5 V.
  • Low input current of 1 μA max 2.

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Datasheet preview – SN54HC112

Datasheet Details

Part number SN54HC112
Manufacturer Texas Instruments
File Size 1.47 MB
Description DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
Datasheet download datasheet SN54HC112 Datasheet
Additional preview pages of the SN54HC112 datasheet.

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Full PDF Text Transcription

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SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 40-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max 2 Description The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse.
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