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SN54HCT00 Datasheet Preview

SN54HCT00 Datasheet

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

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D Operating Voltage Range of 4.5 V to 5.5 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
SN54HCT00 . . . J OR W PACKAGE
SN74HCT00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
SN54HCT00, SN74HCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS062D – NOVEMBER 1988 – REVISED AUGUST 2003
D Typical tpd = 10 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Inputs Are TTL-Voltage Compatible
SN54HCT00 . . . FK PACKAGE
(TOP VIEW)
1Y
3 2 1 20 19
4
18
4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
description/ordering information
NC – No internal connection
These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A B or
Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube of 25
SN74HCT00N
SN74HCT00N
Tube of 50
SN74HCT00D
SOIC – D
Reel of 2500 SN74HCT00DR
HCT00
Reel of 250
SN74HCT00DT
–40°C to 85°C SOP – NS
Reel of 2000 SN74HCT00NSR
HCT00
SSOP – DB
Reel of 2000 SN74HCT00DBR
HT00
Tube of 90
SN74HCT00PW
TSSOP – PW
Reel of 2000 SN74HCT00PWR
HT00
Reel of 250
SN74HCT00PWT
CDIP – J
–55°C to 125°C CFP – W
Tube of 25
Tube of 150
SNJ54HCT00J
SNJ54HCT00W
SNJ54HCT00J
SNJ54HCT00W
LCCC – FK
Tube of 55
SNJ54HCT00FK
SNJ54HCT00FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




etcTI

SN54HCT00 Datasheet Preview

SN54HCT00 Datasheet

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

No Preview Available !

SN54HCT00, SN74HCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS062D – NOVEMBER 1988 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic diagram (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT00
MIN NOM MAX
SN74HCT00
UNIT
MIN NOM MAX
VCC
VIH
VIL
VI
VO
t/v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition rise/fall time
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
4.5
5 5.5 4.5
5 5.5 V
2
2
V
0.8
0.8 V
0
VCC
0
VCC V
0
VCC
0
VCC V
500
500 ns
TA
Operating free-air temperature
–55
125 –40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN54HCT00
Description QUADRUPLE 2-INPUT POSITIVE-NAND GATE
Maker etcTI
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