900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






etcTI

SN54LV166A Datasheet Preview

SN54LV166A Datasheet

8-BIT PARALLEL-LOAD SHIFT REGISTER

No Preview Available !

D 2-V to 5.5-V VCC Operation
D Max tpd of 10.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Ioff Supports Partial-Power-Down-Mode
Operation
D Synchronous Load
SN54LV166A . . . J OR W PACKAGE
SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SER 1
A2
B3
C4
D5
CLK INH 6
CLK 7
GND 8
16 VCC
15 SH/LD
14 H
13 QH
12 G
11 F
10 E
9 CLR
SN54LV166A, SN74LV166A
8ĆBIT PARALLELĆLOAD SHIFT REGISTERS
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
D Direct Overriding Clear
D Parallel-to-Serial Conversion
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV166A . . . FK PACKAGE
(TOP VIEW)
B
3 2 1 20 19
4
18
H
C5
NC 6
17 QH
16 NC
D7
15 G
CLK INH 8
14 F
9 10 11 12 13
description/ordering information
NC − No internal connection
The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 40
Reel of 2500
SN74LV166AD
SN74LV166ADR
LV166A
SOP − NS
Reel of 2000 SN74LV166ANSR 74LV166A
−40°C to 85°C
SSOP − DB
Reel of 2000
Tube of 90
SN74LV166ADBR
SN74LV166APW
LV166A
TSSOP − PW
Reel of 2000
Reel of 250
SN74LV166APWR
SN74LV166APWT
LV166A
TVSOP − DGV Reel of 2000 SN74LV166ADGVR LV166A
CDIP − J
Tube of 25
SNJ54LV166AJ
SNJ54LV166AJ
−55°C to 125°C CFP − W
Tube of 150
SNJ54LV166AW
SNJ54LV166AW
LCCC − FK
Tube of 55
SNJ54LV166AFK
SNJ54LV166AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
1




etcTI

SN54LV166A Datasheet Preview

SN54LV166A Datasheet

8-BIT PARALLEL-LOAD SHIFT REGISTER

No Preview Available !

SN54LV166A, SN74LV166A
8ĆBIT PARALLELĆLOAD SHIFT REGISTERS
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
description/ordering information (continued)
The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input.
When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
CLR
L
H
H
H
H
H
FUNCTION TABLE
INPUTS
SH/LD CLK INH CLK
X
X
X
X
L
L
L
L
H
L
H
L
X
H
SER
X
X
X
H
L
X
PARALLEL
A...H
X
X
a...h
X
X
X
OUTPUTS
INTERNAL
QA
QB
QH
L
QA0
a
H
L
QA0
L
QB0
b
QAn
QAn
QB0
L
QH0
h
QGn
QGn
QH0
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN54LV166A
Description 8-BIT PARALLEL-LOAD SHIFT REGISTER
Maker etcTI
Total Page 3 Pages
PDF Download

SN54LV166A Datasheet PDF

View PDF for Mobile






Similar Datasheet

1 SN54LV166A 8-BIT PARALLEL-LOAD SHIFT REGISTER
etcTI





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy