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SN55115 Datasheet Preview

SN55115 Datasheet

DUAL DIFFERENTIAL RECEIVERS

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SN55115, SN75115
DUAL DIFFERENTIAL RECEIVERS
D Choice of Open-Collector or Active Pullup
(Totem-Pole) Outputs
D Single 5-V Supply
D Differential Line Operation
D Dual-Channel Operation
D TTL Compatible
D ± 15-V Common-Mode Input Voltage Range
D Optional-Use Built-In 130-Line-
Terminating Resistor
D Individual Frequency-Response Controls
D Individual Channel Strobes
D Designed for Use With SN55113, SN75113,
SN55114, and SN75114 Drivers
D Designed to Be Interchangeable With
National DS9615 Line Receivers
SLLS072D – SEPTEMBER 1973 – REVISED MAY 1998
SN55115 . . . J OR W PACKAGE
SN75115 . . . N PACKAGE
(TOP VIEW)
1YS 1
1YP 2
1STRB 3
1RTC 4
1B 5
1RT 6
1A 7
GND 8
16 VCC
15 2YS
14 2YP
13 2STRB
12 2RTC
11 2B
10 2RT
9 2A
SN55114 . . . FK PACKAGE
(TOP VIEW)
description
The SN55115 and SN75115 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise. These devices give TTL-compatible output
signals as a function of the differential input
voltage. The open-collector output configuration
permits the wire-ANDing of similar TTL outputs
(such as SN5401/SN7401) or other
SN55115/SN75115 line receivers. This permits a
level of logic to be implemented without extra
delay.
1STRB
1RTC
NC
1B
1RT
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2YP
2STRB
NC
2RTC
2B
NC – No internal connection
The output stages are similar to TTL totem-pole outputs, but with sink outputs, 1YS and 2YS, and the
corresponding active pullup terminals, 1YP and 2YP, available on adjacent package pins. The frequency
response and noise immunity may be provided by a single external capacitor. A strobe input is provided for each
channel. With the strobe in the low level, the receiver is disabled and the outputs are forced to a high level.
The SN55115 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN75115 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
STRB
DIFF INPUT
(A AND B)
OUTPUT
(YP AND YS
TIED
TOGETHER)
L
X
H
H
L
H
H
H
L
H = VI VIH min or VID more positive than VT + max
L = VI VIL max or VID more negative thanVT max
X = irrelevant
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
1




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SN55115 Datasheet Preview

SN55115 Datasheet

DUAL DIFFERENTIAL RECEIVERS

No Preview Available !

SN55115, SN75115
DUAL DIFFERENTIAL RECEIVERS
SLLS072D – SEPTEMBER 1973 – REVISED MAY 1998
logic symbol
5
1B
&
7
1A
6
1RT 3
RT
1STRB
4
1RTC
RSP
11
2B
9
2A
10
2RT 13
2STRB
12
2RTC
2 1YP
1 1YS
14
2YP
15 2YS
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
5
1B
7
1A
6
1RT 4
1RTC
3
1STRB
11
2B
9
2A
10
2RT 12
2RTC
13
2STRB
2 1YP (Pullup)
1 1YS (Sink)
14 2YP (Pullup)
15 2YS (Sink)
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN55115
Description DUAL DIFFERENTIAL RECEIVERS
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SN55115 Datasheet PDF






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