SN65DP141 Datasheet | Texas Instruments

SLLSES6C - FEBRUARY 2016 - REVISED DECEMBER 2021 SN65DP141 Display Port Linear Redriver 1 Features 3 Description - Supports VESA Display Port 1.4a, 2.0, and e DP 1.4 - Quad channel linear redriver supporting data rates up to 12 Gbps including Display Port RBR, HBR, HBR2, HBR3, and UHBR10 - Protocol agnostic - Transparent to DP link training - Position independent on the link suitable for source, sink, and cable applications - 15-d B analog equalization at 6 GHz - Output linear dynamic range: 1200 m V - Bandwidth: >20 GHz - Better than 16-d B return loss at 6 GHz - 2.5-V or 3.3-V ±5% single power supply option - Low power consumption with 80 m W per channel at 2.5 V VCC - GPIO or I2C control 2 Applications - Tablets - Notebooks - Desktops - Docking stations The SN65DP141 is an asynchronous, protocolagnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps and pensates for losses due to board traces and cables. The device is transparent to Display Port (DP) link training such a way that a DP source and a sink can perform effective link training overing traditional aux snooping re-drivers’ shortings. Additionally, the device is position independent. It can be placed inside source, cable or sink effectively providing a negative loss ponent to the overall link budget. Linear equalization inside SN65DP141 also increases link margin when used with a receiver implementing Decision Feedback Equalization (DFE). SN65DP141 allows independent channel control for equalization, gain, dynamic range using both I2C and GPIO configurations. Device Information(1) PART NUMBER PACKAGE BODY SIZE...