SN65HVD179 Datasheet | Texas Instruments

URES - Designed for INTERBUS Applications - Balanced Receiver Thresholds - 1/2 Unit-Load (up to 64 nodes on the bus) - Bus-Pin ESD Protection 15 k V HBM - Bus-Fault Protection of - 7V to 12V - Thermal Shutdown Protection - Power-Up/Down Glitch-free Bus Inputs and Outputs - Designed for RS-422 and RS-485 Networks APPLICATIONS - Digital Motor Control - Utility Meters - Chassis-to-Chassis Interconnections - Electronic Security Stations - Industrial, Process, and Building Automation - Point-of-Sale (POS) Terminals and Networks - DTE/DCE Interfaces DESCRIPTION The SN65HVD179 is a differential line driver and differential-input line receiver that operates with a 5-V power supply. Each driver and receiver has separate input and output pins for full-duplex bus munication designs. They are designed for balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and ISO 8482:1993 standard-pliant devices. The differential bus driver and receiver are monolithic, integrated circuits designed for full-duplex bi-directional data munication on multipoint bus-transmission lines at signaling rates(1) up to 25 Mbps. The SN65HVD179 is fully enabled with no external enabling pins. The 1/2 unit load receiver has a high receiver input resistance. This results in lower bus leakage currents over the mon-mode voltage range, and reduces the total amount of current that a 485 driver is forced to source or sink when transmitting. The balanced differential receiver input threshold makes the SN65HVD179 fully patible with fieldbus requirements that define an external failsafe structure. (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). -0.20 V -0.15 V -0.10 V -0.05 V 0V 0.05 V 0.10 V 0.15 V 0.20 V BALANCED RECEIVER INPUT THRESHOLDS Recevier Output High VIT- (T Y P ) VIT+ (T Y P ) Receiver Output...