SN65LVDT41-EP Datasheet | Texas Instruments

FEATURES - Controlled Baseline - One Assembly/Test Site, One Fabrication Site - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree (1) - Integrated 110-Ω Nominal Receiver Line Termination Resistor - Operate From a Single 3.3-V Supply - Greater Than 125-Mbps Data Rate - Flow-Through Pinout - LVTTL-patible Logic I/Os - ESD Protection on Bus Pins Exceeds 12 k V - Meet or Exceed Requirements of ANSI/TIA/EIA-644A Standard for LVDS - 20-Pin Thin Shrink Small-Outline Package (PW) With 26-Mil Terminal Pitch (1) ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent...