Datasheet Summary
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Features
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree (1)
- Member of the Texas Instruments
Widebus™ Family
- State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
- Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C
- High-Impedance State During Power Up and Power Down
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (- 32-mA IOH, 64-mA IOL)
- Latch-Up Performance Exceeds 500 mA Per
JESD 70
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