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SN74AHC573-Q1 Datasheet Preview

SN74AHC573-Q1 Datasheet

Octal Transparent D-Type Latche

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SN74AHC573-Q1
www.ti.com.................................................................................................................................................. SCLS697A – DECEMBER 2005 – REVISED APRIL 2008
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
FEATURES
1
Qualified for Automotive Applications
Operating Range 2-V to 5.5-V VCC
3-State Outputs Directly Drive Bus Lines
PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 VCC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
DESCRIPTION
The SN74AHC573 is an octal transparent D-type latch designed for 2-V to 5.5-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
TA
–40°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
TSSOP – PW
Reel of 2000
SN74AHC573QPWRQ1
TOP-SIDE MARKING
HA573Q
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(EACH LATCH)
INPUTS
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
OUTPUT
Q
H
L
Q0
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated




etcTI

SN74AHC573-Q1 Datasheet Preview

SN74AHC573-Q1 Datasheet

Octal Transparent D-Type Latche

No Preview Available !

SN74AHC573-Q1
SCLS697A – DECEMBER 2005 – REVISED APRIL 2008.................................................................................................................................................. www.ti.com
OE 1
LOGIC DIAGRAM (POSITIVE LOGIC)
LE 11
C1
2
1D
1D
19
1Q
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Output voltage range(2)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0 or VO > VCC
IO Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
θJA Package thermal impedance(3)
PW package
Human-Body Model
ESD rating(4)
Charged-Device Model
Machine Model
Tstg Storage temperature range
MIN
MAX UNIT
–0.5
7V
–0.5
7V
–0.5
VCC + 0.5
V
–20 mA
±20 mA
±25 mA
±75 mA
83 °C/W
1 (H1C)
kV
1 (C5)
200 (M3) V
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) ESD protection level per AEC Q100 classification
2
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC573-Q1


Part Number SN74AHC573-Q1
Description Octal Transparent D-Type Latche
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