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SN74AUC00 - QUADRUPLE 2-INPUT POSITIVE-NAND GATE

Datasheet Summary

Description

This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC00 devices perform the Boolean function Y = A ⋅ B or Y = A + B in positive logic.

Features

  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Sub-1-V Operable.
  • Max tpd of 2 ns at 1.8 V.
  • Low Power Consumption, 10-µA Max ICC.
  • ±8-mA Output Drive at 1.8 V.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection Exceeds JESD 22.
  • 2000-V Human-Body Model (A114-A).
  • 200-V Machine Model (A115-A).

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Datasheet Details

Part number SN74AUC00
Manufacturer Texas Instruments
File Size 814.91 KB
Description QUADRUPLE 2-INPUT POSITIVE-NAND GATE
Datasheet download datasheet SN74AUC00 Datasheet
Additional preview pages of the SN74AUC00 datasheet.

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Full PDF Text Transcription

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www.ti.com FEATURES • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 2 ns at 1.8 V • Low Power Consumption, 10-µA Max ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) GND 3Y SN74AUC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES510A – NOVEMBER 2003 – REVISED MARCH 2005 RGY PACKAGE (TOP VIEW) 1A VCC 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 7 14 13 4B 12 4A 11 4Y 10 3B 9 3A 8 DESCRIPTION/ORDERING INFORMATION This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.
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