• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
• Ioff Supports Partial-Power-Down Mode
• Sub-1-V Operable
• Max tpd of 1.9 ns at 1.8 V
• Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES512A – NOVEMBER 2003 – REVISED MARCH 2005
This quadruple 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC08 device performs the Boolean function Y + A • B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
–40°C to 85°C
QFN – RGY
ORDERABLE PART NUMBER
Tape and reel
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated