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SN74AUC126 Datasheet Preview

SN74AUC126 Datasheet

QUADRUPLE BUS BUFFER GATE

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FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
SN74AUC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005
RGY PACKAGE
(TOP VIEW)
1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
7
14
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V
to 1.95-V VCC operation.
The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
QFN – RGY
PACKAGE (1)
Tape and reel
ORDERABLE PART NUMBER
SN74AUC126RGYR
TOP-SIDE MARKING
MS126
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
A
H
H
H
L
L
X
OUTPUT
Y
H
L
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated




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SN74AUC126 Datasheet Preview

SN74AUC126 Datasheet

QUADRUPLE BUS BUFFER GATE

No Preview Available !

SN74AUC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005
1OE 1
2
1A
LOGIC DIAGRAM (POSITIVE LOGIC)
3OE 10
3
1Y
9
3A
2OE 4
5
2A
6
2Y
4OE 13
12
4A
www.ti.com
8
3Y
11
4Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(3)
Tstg Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
47
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
2


Part Number SN74AUC126
Description QUADRUPLE BUS BUFFER GATE
Maker etcTI
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