SN74AUC32 Datasheet | Texas Instruments

Features - Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation - Ioff Supports Partial-Power-Down Mode Operation - Sub-1-V Operable - Max tpd of 2.2 ns at 1.8 V - Low Power Consumption, 10-µA Max ICC - ±8-m A Output Drive at 1.8 V - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) GND 3Y SN74AUC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES513A - NOVEMBER 2003 - REVISED MARCH 2005 RGY PACKAGE (TOP VIEW) 1A VCC 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 14 13 4B 12 4A 11 4Y 10 3B 9 3A DESCRIPTION/ORDERING INFORMATION This quadruple 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC32 device performs the Boolean function Y + A ) B or Y + A - B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. - 40°C to 85°C - RGY ORDERING...