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SN74AUC32374 Datasheet Preview

SN74AUC32374 Datasheet

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

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FEATURES
Member of the Texas Instruments Widebus+™
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
SN74AUC32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES475 – AUGUST 2003 – REVISED MAY 2005
Max tpd of 2.8 ns at 1.8 V
Low Power Consumption, 40-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
LFBGA – GKE Tape and reel SN74AUC32374GKER
TOP-SIDE MARKING
MM374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated




etcTI

SN74AUC32374 Datasheet Preview

SN74AUC32374 Datasheet

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

No Preview Available !

SN74AUC32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES475 – AUGUST 2003 – REVISED MAY 2005
GKE PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS
1
2
3
4
5
A
1Q2
1Q1
1OE
1CLK
1D1
B
1Q4
1Q3
GND
GND
1D3
C
1Q6
1Q5
VCC
VCC
1D5
D
1Q8
1Q7
GND
GND
1D7
E
2Q2
2Q1
GND
GND
2D1
F
2Q4
2Q3
VCC
VCC
2D3
G
2Q6
2Q5
GND
GND
2D5
H
2Q7
2Q8
2OE
2CLK
2D8
J
3Q2
3Q1
3OE
3CLK
3D1
K
3Q4
3Q3
GND
GND
3D3
L
3Q6
3Q5
VCC
VCC
3D5
M
3Q8
3Q7
GND
GND
3D7
N
4Q2
4Q1
GND
GND
4D1
P
4Q4
4Q3
VCC
VCC
4D3
R
4Q6
4Q5
GND
GND
4D5
T
4Q7
4Q8
4OE
4CLK
4D8
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6
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
2


Part Number SN74AUC32374
Description 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Maker etcTI
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