Click to expand full text
www.ti.com
FEATURES
• Member of the Texas Instruments Widebus+™ Family
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
SN74AUC32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES475 – AUGUST 2003 – REVISED MAY 2005
• Max tpd of 2.8 ns at 1.8 V • Low Power Consumption, 40-µA Max ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II • ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.
SN74AUC32374 Datasheet
