SN74AUC74 - DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Product Overview

Texas Instruments

Datasheet Details

Part number	SN74AUC74
Manufacturer	Texas Instruments
File Size	859.27 KB
Description	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Datasheet	SN74AUC74 Datasheet
Additional preview pages of the SN74AUC74 datasheet.

Product details

Description

ORDERING INFORMATION This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.Clock triggering oc

Features

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation.
Ioff Supports Partial-Power-Down Mode Operation.
Sub-1-V Operable.
Max tpd of 1.8 ns at 1.8 V.
Low Power Consumption, 10-µA Max ICC.
±8-mA Output Drive at 1.8 V.
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
ESD Protection Exceeds JESD 22.
2000-V Human-Body Model (A114-A).
200-V Machine Model (A115-.

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Other Datasheets by Texas Instruments

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Published: Aug 31, 2021 |