SN74AUP1G02 Overview
This single 2-input positive-NOR gate performs the Boolean function Y = A + B or Y = A × B in positive logic. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. SN74AUP1G02 SCES568I JUNE 2004 REVISED SEPTEMBER 2016 .ti.
SN74AUP1G02 Key Features
- 1 Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
- Low Static-Power Consumption (ICC = 0.9 μA Max)
- Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V)
- Low Input Capacitance (Ci = 1.5 pF Typ)
- Low Noise
- Overshoot and Undershoot
- Ioff Supports Live Insertion, Partial-Power-Down
- Input Hysteresis Allows Slow Input Transition and
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
SN74AUP1G02 Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22