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SN74AUP1G125 Datasheet Preview

SN74AUP1G125 Datasheet

Low-Power Single Bus Buffer Gate

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SN74AUP1G125
SCES595N – JULY 2004 – REVISED JULY 2017
SN74AUP1G125 Low-Power Single Bus Buffer Gate With 3-State Output
1 Features
1 Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
• Low Dynamic-Power Consumption
(Cpd = 4 pF Typical at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot
< 10% of VCC
• Input-Disable Feature Allows Floating Input
Conditions
• Ioff Supports Partial-Power-Down Mode Operation
• Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at Input
• Wide Operating VCC Range of 0.8 V to 3.6 V
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• tpd = 4.6 ns Maximum at 3.3 V
2 Applications
• Audio Dock: Portable
• BluRay™ Players and Home Theaters
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid-State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Wireless Headsets, Keyboards, and Mice
3 Description
The SN74AUP1G125 bus buffer gate is a single line
driver with a 3-state output. The output is disabled
when the output-enable (OE) input is high. This
device has the input-disable feature, which allows
floating input signals.
To ensure the high-impedance state during power up
or power down, OE must be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G125DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUP1G125DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1G125DRL SOT (5)
1.60 mm × 1.20 mm
SN74AUP1G125DRY
SON (6)
SN74AUP1G125DSF
1.45 mm × 1.00 mm
1.00 mm × 1.00 mm
SN74AUP1G125YFP DSBGA (6)
0.76 mm × 1.16 mm
SN74AUP1G125YZP DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G125YZT DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G125DPW X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1
OE
2
A
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.




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SN74AUP1G125 Datasheet Preview

SN74AUP1G125 Datasheet

Low-Power Single Bus Buffer Gate

No Preview Available !

SN74AUP1G125
SCES595N – JULY 2004 – REVISED JULY 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics, TA = 25°C ........................ 6
6.6 Electrical Characteristics, TA = –40°C to +85°C ....... 7
6.7 Switching Characteristics, CL = 5 pF ........................ 8
6.8 Switching Characteristics, CL = 10 pF ...................... 9
6.9 Switching Characteristics, CL = 15 pF .................... 10
6.10 Switching Characteristics, CL = 30 pF .................. 11
6.11 Operating Characteristics...................................... 12
6.12 Typical Characteristics .......................................... 12
7 Parameter Measurement Information ................ 13
8 Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9 Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 20
12.1 Documentation Support ........................................ 20
12.2 Receiving Notification of Documentation Updates 20
12.3 Community Resources.......................................... 20
12.4 Trademarks ........................................................... 20
12.5 Electrostatic Discharge Caution ............................ 20
12.6 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (December 2015) to Revision N
Page
• Added DPW (X2SON) package.............................................................................................................................................. 1
• Deleted Device Comparison table, see Mechanical, Packaging, and Orderable Information section at the end of the
data sheet ............................................................................................................................................................................... 1
• Changed Simplified Schematic with a new schematic ........................................................................................................... 1
• Added column for X2SON (DPW) package and separated columns for DSBGA packages in Pin Functions table .............. 3
• Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), and Over-voltage Tolerant Inputs ................................................................................................................................. 15
• Added Trace Example and revised Layout Guidelines ........................................................................................................ 18
• Added Receiving Notification of Documentation Updates section ....................................................................................... 20
Changes from Revision L (February 2013) to Revision M
Page
• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision K (November 2012) to Revision L
Page
• Changed Y to Y for pin 4 in DSF Package pin out ................................................................................................................ 3
2
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Description Low-Power Single Bus Buffer Gate
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