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SN74AUP1G80 Datasheet Preview

SN74AUP1G80 Datasheet

Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

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SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
1 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
• Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typical at 3.3 V)
• Low Input Capacitance (Ci = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot <10% of
VCC
• Ioff Supports Partial-Power-Down Mode Operation
• Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at
the Input
(Vhys = 250 mV Typical at 3.3 V)
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• tpd = 4.4 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications
2 Applications
• Home Automation
• Factory Automation
• Test and Measurement
• Enterprise Switching
• Telecom Infrastructure
• Personal Electronics
• White Goods
3 Description
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assures a low static-
and dynamic-power consumption across the entire
VCC range of 0.8 V to 3.6 V, resulting in increased
battery life (see AUP – The Lowest-Power Family).
This product also maintains excellent signal integrity
(see Excellent Signal Integrity).
This is a single positive-edge-triggered D-type flip-
flop. When data at the data (D) input meets the setup
time requirement, the data is transferred to the Q
output on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the D input
can be changed without affecting the levels at the
outputs.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G80DBV SOT-23 (5)
1.60 mm × 2.90 mm
SN74AUP1G80DCK SC70 (5)
1.25 mm × 2.00 mm
SN74AUP1G80DRY SON (6)
1.00 mm × 1.45 mm
SN74AUP1G80DSF SON (6)
1.00 mm × 1.00 mm
SN74AUP1G80YFP DSBGA (6)
0.76 mm × 1.16 mm
SN74AUP1G80YZP DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G80DPW X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
CLK
D
CLK
Q
Q
D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




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SN74AUP1G80 Datasheet Preview

SN74AUP1G80 Datasheet

Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

No Preview Available !

SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics: TA = 25°C ........................ 6
6.6 Electrical Characteristics: TA = –40°C to +85°C ....... 7
6.7 Timing Requirements ................................................ 7
6.8 Switching Characteristics: CL = 5 pF ........................ 8
6.9 Switching Characteristics: CL = 10 pF ...................... 9
6.10 Switching Characteristics: CL = 15 pF .................... 9
6.11 Switching Characteristics: CL = 30 pF .................. 10
6.12 Operating Characteristics...................................... 11
6.13 Typical Characteristics .......................................... 11
7 Parameter Measurement Information ................ 12
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Duration ......................................................... 12
7.2 Enable and Disable Times ...................................... 13
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Documentation Support ........................................ 18
12.2 Receiving Notification of Documentation Updates 18
12.3 Community Resources.......................................... 18
12.4 Trademarks ........................................................... 18
12.5 Electrostatic Discharge Caution ............................ 18
12.6 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2010) to Revision F
Page
• Added DPW (X2SON) package.............................................................................................................................................. 1
• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
• Added Junction temperature, TJ in Absolute Maximum Ratings table ................................................................................... 4
2
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Copyright © 2004–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G80


Part Number SN74AUP1G80
Description Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
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