Datasheet4U Logo Datasheet4U.com

SN74AUP1T14 - SCHMITT-TRIGGER INVERTER GATE

Description

The SN74AUP1T14 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in operating.

Features

  • 1.
  • Single-Supply Voltage Translator.
  • Output Level Up to Supply VCC CMOS Level.
  • 1.8 V to 3.3 V (at VCC = 3.3 V).
  • 2.5 V to 3.3 V (at VCC = 3.3 V).
  • 1.8 V to 2.5 V (at VCC = 2.5 V).
  • 3.3 V to 2.5 V (at VCC = 2.5 V.
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity.
  • Ioff Supports Partial Power Down (VCC = 0 V).
  • Very Low Static Power Consumption: 0.1 µA.
  • Very Low Dynamic Power Co.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SN74101 AND-OR Gate ETC
SN74102 AND Gate ETC
SN74103 Dual J-K Flip-Flop ETC
SN74106 Dual J-K Flip-Flop ETC
SN74108 Dual J-K Flip Flop ETC

Other Datasheets by Texas Instruments

Part Number Description
SN74AUP1T157 SCHMITT-TRIGGER BUFFER MULTIPLEXER
SN74AUP1T158 SCHMITT-TRIGGER BUFFER MULTIPLEXER
SN74AUP1T17 Single Schmitt-Trigger Buffer Gate
SN74AUP1T00 POSITIVE-NAND GATE
SN74AUP1T02 POSITIVE-NOR GATE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SN74AUP1T14 www.ti.com SCES802 – APRIL 2010 LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE Check for Samples: SN74AUP1T14 FEATURES 1 • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at VCC = 2.5 V) – 3.3 V to 2.5 V (at VCC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity • Ioff Supports Partial Power Down (VCC = 0 V) • Very Low Static Power Consumption: 0.1 µA • Very Low Dynamic Power Consumption: 0.9 µA • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.1 mm) • More Gate Options Available at www.ti.
Published: |