SN74AUP1T14 Datasheet | Texas Instruments

.ti. SCES802 - APRIL 2010 LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE Check for Samples: SN74AUP1T14 Features - Single-Supply Voltage Translator - Output Level Up to Supply VCC CMOS Level - 1.8 V to 3.3 V (at VCC = 3.3 V) - 2.5 V to 3.3 V (at VCC = 3.3 V) - 1.8 V to 2.5 V (at VCC = 2.5 V) - 3.3 V to 2.5 V (at VCC = 2.5 V - Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity - Ioff Supports Partial Power Down (VCC = 0 V) - Very Low Static Power Consumption: 0.1 µA - Very Low Dynamic Power Consumption: 0.9 µA - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.1 mm) - More Gate Options Available at .ti./littlelogic - ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) V CC DESCRIPTION/ORDERING INFORMATION The SN74AUP1T14 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC. AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors. Schmitt-trigger inputs (ΔVT = 210 m V between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal...