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SN74HC112N - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

Download the SN74HC112N datasheet PDF. This datasheet also covers the SN74HC112 variant, as both devices belong to the same dual j-k negative-edge-triggered flip-flops family and are provided as variant models within a single manufacturer datasheet.

General Description

The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

Key Features

  • Wide operating voltage range of 2 V to 6 V.
  • Outputs can drive up to 10 LSTTL loads.
  • Low power consumption, 40-μA max ICC.
  • Typical tpd = 13 ns.
  • ±4-mA output drive at 5 V.
  • Low input current of 1 μA max 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN74HC112-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
SN74HC11 Triple 3-Input AND Gates
SN74HC10 Triple 3-Input NAND Gates
SN74HC10-EP TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74HC10-Q1 TRIPLE 3-INPUT POSITIVE-NAND GATE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 40-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max 2 Description The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse.