SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITTĆTRIGGER INPUTS
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In
circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
(each monostable multivibrator)
CLR A B Q Q
XHX L H
† Pulsed-output patterns are tested during
AC switching at 25°C with Rext = 2 kΩ, and
Cext = 80 pF.
‡ This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).
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