QUADRUPLE 2-INPUT POSITIVE-AND GATE
D Qualified for Automotive Applications
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Supports Mixed-Mode Voltage Operation on
D Ioff Supports Partial-Power-Down Mode
D Latch-Up Performance Exceeds 250 mA Per
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV08A performs the Boolean function Y + A • B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
−40°C to 105°C TSSOP − PW Tape and reel SN74LV08ATPWRQ1 LV08ATQ
† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
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testing of all parameters.
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