900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






etcTI

SN74LVC00A-EP Datasheet Preview

SN74LVC00A-EP Datasheet

Quadruple 2-Input Positive-NAND Gate

No Preview Available !

www.ti.com
FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –40°C
to 125°C and –55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC00A-EP
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SCAS729B – NOVEMBER 2003 – REVISED MARCH 2007
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
D OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
The SN74LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V VCC operation.
The device performs the Boolean function Y = A B or Y = A + B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION(1)
TA
–40 °C to 125 °C
–55 °C to 125 °C
SOIC – D
TSSOP – PW
TSSOP – PW
PACKAGE (2)
Reel of 2500
Reel of 2000
Reel of 2000
ORDERABLE PART NUMBER
SN74LVC00AQDREP
SN74LVC00AQPWREP
SN74LVC00AMPWREP
TOP-SIDE MARKING
LVC00AE
LVC00AE
LVC00AM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.




etcTI

SN74LVC00A-EP Datasheet Preview

SN74LVC00A-EP Datasheet

Quadruple 2-Input Positive-NAND Gate

No Preview Available !

SN74LVC00A-EP
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SCAS729B – NOVEMBER 2003 – REVISED MARCH 2007
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Output voltage range(2)(3)
IIK
Input clamp current
VI < 0 V
IOK
Output clamp current
VO < 0 V
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
D package
PW package
Tstg
Storage temperature range
MIN
MAX UNIT
–0.5
6.5 V
–0.5
6.5 V
–0.5
VCC + 0.5 V
–50 mA
–50 mA
±50 mA
±100 mA
86
°C/W
113
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
Operating
Data retention only
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
VCC = 2.7 V
VCC = 3 V
VCC = 2.7 V
VCC = 3 V
M suffix
Q suffix
MIN MAX UNIT
2 3.6
V
1.5
2
V
0.8 V
0 5.5 V
0 VCC
V
–12
mA
–24
12
mA
24
–55 125
°C
–40 125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
Submit Documentation Feedback


Part Number SN74LVC00A-EP
Description Quadruple 2-Input Positive-NAND Gate
Maker etcTI
PDF Download

SN74LVC00A-EP Datasheet PDF






Similar Datasheet

1 SN74LVC00A-EP Quadruple 2-Input Positive-NAND Gate
etcTI





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy