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SN74LVC32374A Datasheet Preview

SN74LVC32374A Datasheet

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

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FEATURES
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C
SN74LVC32374A
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES407A – JULY 2002 – REVISED MARCH 2005
Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input and Output Voltages With
3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
LFBGA – GKE
LFBGA – ZKE (Pb-free)
Tape and reel
SN74LVC32374AGKER
SN74LVC32374AZKER
TOP-SIDE MARKING
NC374A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated




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SN74LVC32374A Datasheet Preview

SN74LVC32374A Datasheet

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

No Preview Available !

SN74LVC32374A
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES407A – JULY 2002 – REVISED MARCH 2005
GKE OR ZKE PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
A
1Q2
B
1Q4
C
1Q6
D
1Q8
E
2Q2
F
2Q4
G
2Q6
H
2Q7
J
3Q2
K
3Q4
L
3Q6
M
3Q8
N
4Q2
P
4Q4
R
4Q6
T
4Q7
TERMINAL ASSIGNMENTS
2
3
4
5
1Q1
1OE
1CLK
1D1
1Q3
GND
GND
1D3
1Q5
VCC
VCC
1D5
1Q7
GND
GND
1D7
2Q1
GND
GND
2D1
2Q3
VCC
VCC
2D3
2Q5
GND
GND
2D5
2Q8
2OE
2CLK
2D8
3Q1
3OE
3CLK
3D1
3Q3
GND
GND
3D3
3Q5
VCC
VCC
3D5
3Q7
GND
GND
3D7
4Q1
GND
GND
4D1
4Q3
VCC
VCC
4D3
4Q5
GND
GND
4D5
4Q8
4OE
4CLK
4D8
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6
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
2


Part Number SN74LVC32374A
Description 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
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