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SN74LVC373A-Q1 Datasheet Preview

SN74LVC373A-Q1 Datasheet

OCTAL TRANSPARENT D-TYPE LATCH

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SN74LVC373A-Q1
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS710B – SEPTEMBER 2003 – REVISED FEBRUARY 2008
FEATURES
1
Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 7.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
DW OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
DESCRIPTION/ORDERING INFORMATION
The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
TA
–40°C to 125°C
SOIC – DW
TSSOP – PW
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Reel of 2000
SN74LVC373AQDWRQ1
Reel of 2000
SN74LVC373AQPWRQ1
TOP-SIDE MARKING
L373AQ1
L373AQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated




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SN74LVC373A-Q1 Datasheet Preview

SN74LVC373A-Q1 Datasheet

OCTAL TRANSPARENT D-TYPE LATCH

No Preview Available !

SN74LVC373A-Q1
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS710B – SEPTEMBER 2003 – REVISED FEBRUARY 2008
FUNCTION TABLE
(EACH LATCH)
INPUTS
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
OUTPUT
Q
H
L
Q0
Z
OE 1
LOGIC DIAGRAM (POSITIVE LOGIC)
LE 11
C1
3
1D
1D
2
1Q
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To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Voltage range applied to any output in the high or low state(2)(3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(4)
DW package
PW package
Tstg
Storage temperature range
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5
6.5
–0.5 VCC + 0.5
–50
–50
±50
±100
58
83
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC373A-Q1



Part Number SN74LVC373A-Q1
Description OCTAL TRANSPARENT D-TYPE LATCH
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