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SN74LVCH16646A Datasheet Preview

SN74LVCH16646A Datasheet

16-BIT BUS TRANSCEIVER/REGISTER

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www.ti.com
FEATURES
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.7 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage
With 3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 16-bit bus transceiver and register is designed
for 1.65-V to 3.6-V VCC operation.
The SN74LVCH16646A can be used as two 8-bit
transceivers or one 16-bit transceiver. The device
consists of bus transceiver circuits, D-type flip-flops,
and control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318K – NOVEMBER 1993 – REVISED MARCH 2005
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR 1
1CLKAB 2
1SAB 3
GND 4
1A1 5
1A2 6
VCC 7
1A3 8
1A4 9
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
VCC 22
2A7 23
2A8 24
GND 25
2SAB 26
2CLKAB 27
2DIR 28
56 1OE
55 1CLKBA
54 1SBA
53 GND
52 1B1
51 1B2
50 VCC
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
35 VCC
34 2B7
33 2B8
32 GND
31 2SBA
30 2CLKBA
29 2OE
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
SSOP – DL
Tube
Tape and reel
SN74LVCH16646ADL
SN74LVCH16646ADLR
TSSOP – DGG Tape and reel
SN74LVCH16646ADGGR
TVSOP – DGV Tape and reel
SN74LVCH16646ADGVR
TOP-SIDE MARKING
LVCH16646A
LVCH16646A
LDH646A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated




etcTI

SN74LVCH16646A Datasheet Preview

SN74LVCH16646A Datasheet

16-BIT BUS TRANSCEIVER/REGISTER

No Preview Available !

SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318K – NOVEMBER 1993 – REVISED MARCH 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with
the SN74LVCH16646A.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and
SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control
eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and
real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data
can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
FUNCTION TABLE
INPUTS
DATA I/O(1)
OE
DIR CLKAB CLKBA SAB SBA
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
H or L H or L
X
X
A1–A8
Input
Unspecified
Input
Input
B1–B8
Unspecified
Input
Input
Input
L
L
X
X
X
L
Output
Input
L
L
X
H or L
X
H
Output
Input
L
H
X
X
L
X
Input
Output
L
H
H or L
X
H
X
Input
Output
OPERATION OR FUNCTION
Store A, B unspecified(1)
Store B, A unspecified(1)
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
(1) The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2



Part Number SN74LVCH16646A
Description 16-BIT BUS TRANSCEIVER/REGISTER
Maker etcTI
Total Page 3 Pages
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