D 1-to-2 Outputs Support Stacked DDR DIMMs D One Device Per DIMM Required D Output Edge-Control Circuitry Minimizes Swit.

ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, .

SN74SSTVF16857

SN74SSTVF16859

SN74SSTV16859

SN74SSTV32852

SN74SSTV32852-EP

SN74SSTV32867-EP

SN74SSTEB32866

SN74SSTU32864

SN74SSTU32864C

SN74SSTUB32864

SN74SSTUB32866

SN74SSQE32882

SN74SSQEA32882

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