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SN75C1154 Datasheet Preview

SN75C1154 Datasheet

QUADRUPLE LOW-POWER DRIVERS/RECEIVERS

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SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
D Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
D Very Low Power Consumption . . .
5 mW Typ
D Wide Driver Supply Voltage . . .
±4.5 V to ±15 V
D Driver Output Slew Rate Limited to
30 V/µs Max
D Receiver Input Hysteresis . . . 1000 mV Typ
D Push-Pull Receiver Outputs
D On-Chip Receiver 1-µs Noise Filter
description/ordering information
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
SN65C1154 . . . N PACKAGE
SN75C1154 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
VDD 1
1RA 2
1DY 3
2RA 4
2DY 5
3RA 6
3DY 7
4RA 8
4DY 9
VSS 10
20 VCC
19 1RY
18 1DA
17 2RY
16 2DA
15 3RY
14 3DA
13 4RY
12 4DA
11 GND
The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and
receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment
(DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154
and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver,
respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the
receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need
for external components.
The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology.
In most applications, the receivers contained in these devices interface to single inputs of peripheral devices
such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive
to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the
SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the
HCMOS, ALS, or 74F logic families.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C
PDIP (N)
Tube of 20
SN65C1154N
SN65C1154N
PDIP (N)
Tube of 20
SN75C1154N
SN75C1154N
0°C to 70°C
SOIC (DW)
Tube of 25
Reel of 2500
SN75C1154DW
SN75C1154DWR
SN75C1154
SOP (NS)
Reel of 2000 SN75C1154NSR
SN75C1154
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1




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SN75C1154 Datasheet Preview

SN75C1154 Datasheet

QUADRUPLE LOW-POWER DRIVERS/RECEIVERS

No Preview Available !

SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D DECEMBER 1988 REVISED APRIL 2003
logic diagram (positive logic)
Typical of Each Receiver
2, 4, 6, 8
RA
19, 17, 15, 13
RY
Typical of Each Driver
3, 5, 7, 9
DY
18, 16, 14, 12
DA
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN75C1154
Description QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
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