SN75LBC175A Datasheet Text
SN65LBC175A, SN75LBC175A QUADRUPLE RSĆ485 DIFFERENTIAL LINE RECEIVERS
SLLS455C
- NOVEMBER 2000
- REVISED MARCH 2009
D Designed for TIA/EIA-485, TIA/EIA-422, and
ISO 8482 Applications
D Signaling Rate1 Exceeding 50 Mbps D Fail-Safe in Bus Short-Circuit, Open-Circuit, and Idle-Bus Conditions
D ESD Protection on Bus Inputs 6 kV D mon-Mode Bus Input Range
- 7 V to 12 V
D Propagation Delay Times <16 ns D Low Standby Power Consumption <20 µA D Pin-patible Upgrade for MC3486,
DS96F175, LTC489, and SN75175
SN65LBC175A (Marked as 65LBC175A) SN75LBC175A (Marked as 75LBC175A)
D or N PACKAGE (TOP VIEW)
1B 1 1A 2 1Y 3 1,2EN 4 2Y 5 2A 6 2B 7 GND 8
16 VCC 15 4B 14 4A 13 4Y 12 3,4EN 11 3Y 10 3A 9 3B logic diagram description
1,2EN
The SN65LBC175A and SN75LBC175A are quadruple differential line receivers with 3-state
1A
1Y outputs, designed for TIA/EIA-485 (RS-485),
1B
TIA/EIA-422 (RS-422), and ISO 8482 (Euro
RS-485) applications.
2A
These devices are optimized for balanced
2B
2Y multipoint bus munication at data rates up to and exceeding 50 million bits per second. The
3,4EN transmission media may be twisted-pair cables,
3A printed-circuit board traces, or backplanes. The
3Y ultimate rate and distance of data transfer is
3B dependent upon the attenuation characteristics of the media and the noise coupling to the...