TAS5076
Key Features
- unctional 2 Architecture Overview
- 2.1 Clock and Serial Data Interface
- 2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
- 2.1.2 Clock Master/Slave Mode (M_S)
- 2.1.3 Clock Master Mode
- 2.1.4 Clock Slave Mode
- 2.1.5 PLL External Filter
- 2.1.7 Serial Data Interface
- 2.2 Reset, Power Down, and Status
- 2.2.2 Power Down—PDN
