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TDA4VM Datasheet

Automotive Processor

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TDA4VM
SPRSP36E – FEBRUARY 2019 – REVISED DECEMBER 2019
TDA4VM Jacinto™ Automotive Processors
for ADAS and Autonomous Vehicles
Silicon Revision 1.0
1 Device Overview
1.1 Features
1Processor cores:
• C7x floating point, vector DSP, up to 1.0 GHz, 80
GFLOPS, 256 GOPS
• Deep-learning matrix multiply accelerator (MMA),
up to 8 TOPS (8b) at 1.0 GHz
• Vision Processing Accelerators (VPAC) with Image
Signal Processor (ISP) and multiple vision assist
accelerators
• Depth and Motion Processing Accelerators
(DMPAC)
• Dual 64-bit Arm® Cortex®-A72 microprocessor
subsystem at up to 1.8 GHz, 22K DMIPS
– 1MB shared L2 cache per dual-core Cortex®-
A72 cluster
– 32KB L1 DCache and 48KB L1 ICache per
Cortex®-A72 core
• Six Arm® Cortex®-R5F MCUs at up to 1.0 GHz,
12K DMIPS
– 64K L2 RAM per core memory
– Two Arm® Cortex®-R5F MCUs in isolated MCU
subsystem
– Four Arm® Cortex®-R5F MCUs in general
compute partition
• Two C66x floating point DSP, up to 1.35 GHz,
40 GFLOPS, 160 GOPS
• 3D GPU PowerVR® Rogue 8XE GE8430, up to
750 MHz, 96 GFLOPS, 6 Gpix/sec
• Custom-designed interconnect fabric supporting
near max processing entitlement
Memory subsystem:
• Up to 8MB of on-chip L3 RAM with ECC and
coherency
– ECC error protection
– Shared coherent cache
– Supports internal DMA engine
• External Memory Interface (EMIF) module with
ECC
– Supports LPDDR4 memory types
– Supports speeds up to 3733 MT/s
– 32-bit data bus with inline ECC up to 14.9GB/s
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected
by ECC
Safety: targeted to meet ASIL-D for MCU island
and ASIL-B for main processor
• Integrated MCU island subsystem of Dual Arm®
Cortex®-R5F cores with floating point coprocessor
and optional lockstep operation, targeted to meet
ASIL-D safety requirements/certification
– 512B Scratchpad RAM memory
– Up to 1MB on-chip RAM with ECC dedicated for
R5F
– Integrated Cortex®-R5F MCU island isolated on
separate voltage and clock domains
– Dedicated memory and interfaces capable of
being isolated from the larger SoC
• The TDA4VM main processor is targeted to meet
ASIL-B safety requirements/certification
– Widespread ECC protection of on-chip memory
and interconnect
– Built-in self-test (BIST) and fault-injection for
CPU and on-chip RAM
– Error Signaling Module (ESM) with error pin
– Runtime safety diagnostics, voltage,
temperature, and clock monitoring, windowed
watchdog timers, CRC engine for memory
integrity checks
– Safety documentation available for applications
required to meet ISO 26262 requirements
Device security:
• Secure boot with secure runtime support
• Customer programmable root key, up to RSA-4K
or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC,
AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
• Integrated ethernet switch supporting
(total of 8 external ports)
– Up to eight 2.5Gb SGMII
– Up to eight RMII (10/100) or RGMII
(10/100/1000)
– Up to two QSGMII
• Up to four PCI-Express® (PCIe) Gen3 controllers
– Up to two lanes per controller
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.




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TDA4VM Datasheet Preview

TDA4VM Datasheet

Automotive Processor

No Preview Available !

TDA4VM
SPRSP36E – FEBRUARY 2019 – REVISED DECEMBER 2019
– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
(8.0GT/s) operation with auto-negotiation
• Two USB 3.0 dual-role device (DRD) subsystem
– Two enhanced SuperSpeed Gen1 Ports
– Each port supports Type-C switching
– Each port independently configurable as USB
host, USB peripheral, or USB DRD
Automotive interfaces:
• Sixteen Modular Controller Area Network (MCAN)
modules with full CAN-FD support
Capture subsystem:
• Two CSI2.0 4L RX plus One CSI2.0 4L TX
– 2.5Gbps RX throughput per lane (20Gbps total)
Display subsystem:
• One eDP/DP interface with Multi-Display Support
(MST)
– HDCP1.4/HDCP2.2 high-bandwidth digital
content protection
• One DSI TX (up to 2.5K)
• Up to two DPI
Audio interfaces:
• Twelve Multichannel Audio Serial Port (MCASP)
modules
1.2 Applications
Advanced surround view and park assistance
systems
Autonomous sensor fusion / perception systems
including camera, radar and lidar sensors
www.ti.com
Video acceleration:
• Ultra-HD video, one (3840 × 2160p, 60 fps), or two
(3840 × 2160p, 30 fps) H.264/H.265 decode
• Full-HD video, four (1920 × 1080p, 60 fps), or eight
(1920 × 1080p, 30 fps) H.264/H.265 decode
• Full-HD video, one (1920 × 1080p, 60 fps), or up
to three (1920 × 1080p, 30 fps) H.264 encode
Flash memory interfaces:
• Embedded MultiMediaCard Interface ( eMMC™
5.1)
• Universal Flash Storage (UFS 2.1) interface with
two lanes
• Two Secure Digital® 3.0/Secure Digital Input
Output 3.0 interfaces (SD3.0/SDIO3.0)
• Two simultaneous flash interfaces configured as
– One OSPI and one QSPI flash interfaces
– or HyperBus™ and QSPI flash interface
System-on-Chip (SoC) architecture:
• 16-nm FinFET technology
• 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA
(ALF), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management
ICs (PMIC):
• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases
Mono and multi-sensor Front camera systems
Next generation eMirror systems
2
Device Overview
Submit Documentation Feedback
Product Folder Links: TDA4VM
Copyright © 2019, Texas Instruments Incorporated



Part Number TDA4VM
Description Automotive Processor
Maker etcTI
Total Page 3 Pages
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