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TL16C554FN Datasheet Preview

TL16C554FN Datasheet

ACE

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ąą
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
ą
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
D Integrated Asynchronous Communications
Element
D Consists of Four Improved TL16C550 ACEs
Plus Steering Logic
D In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
D In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
D Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
D Programmable Baud Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216ā ā 1) and
Generate an Internal 16 × Clock
D Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
D Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D Fully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (DC to 1-Mbit Per
Second)
D False Start Bit Detection
D Complete Status Reporting Capabilities
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D 3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
description
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the operation performed and
any error conditions encountered.
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and
(216 −1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and
in an 80-pin (TQFP) PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1994 − 2006, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




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TL16C554FN Datasheet Preview

TL16C554FN Datasheet

ACE

No Preview Available !

TL16C554, TL16C554I
ą
ASYNCHRONOUS COMMUNICATIONS ELEMENT
ą
SLLS165G − JANUARY 1994 − REVISED MARCH 2006
FN PACKAGE
(TOP VIEW)
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
NC − No internal connection
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number TL16C554FN
Description ACE
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