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TL16C750 Datasheet Preview

TL16C750 Datasheet

ACE

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
D Pin-to-Pin Compatible With the Existing
TL16C550B/C
D Programmable 16- or 64-Byte FIFOs to
Reduce CPU Interrupts
D Programmable Auto-RTS and Auto-CTS
D In Auto-CTS Mode, CTS Controls
Transmitter
D In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
D Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
D In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16 ×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream
D 5-V and 3-V Operation
D Register Selectable Sleep Mode and
Low-Power Mode
D Independent Receiver Clock Input
D Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbits Per
Second)
D False Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State Output CMOS Drive Capabilities for
Bidirectional Data Bus and Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Available in 44-Pin PLCC and 64-Pin SQFP
D Industrial Temperature Range Available for
64-Pin SQFP
description
The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up
(character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO
mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.
The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte
for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode.
In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload
and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS
input signals (see Figure 1).
The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The
ACE includes complete modem control capability and a processor interrupt system that can be tailored to
minimize software management of the communications link.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1




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TL16C750 Datasheet Preview

TL16C750 Datasheet

ACE

No Preview Available !

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
description (continued)
The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by
divisors from 1 to (216 – 1) and producing a 16 × reference clock for the internal transmitter logic. Provisions are
also included to use this 16 × clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate
(16-MHz input clock) so a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions have been changed to TXRDY and RXRDY, which provide signaling
to a direct memory access (DMA) controller.
FN PACKAGE
(TOP VIEW)
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
A2
PM PACKAGE
(TOP VIEW)
XIN
XOUT
NC
WR1
NC
WR2
NC
VSS
RD1
RD2
NC
DDIS
TXRDY
NC
ADS
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D4
NC
D3
D2
NC
D1
D0
NC
VCC
NC
RI
NC
DCD
DSR
NC
CTS
NC – No internal connection
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number TL16C750
Description ACE
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