TLV320AIC15 Overview
.ti. TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E OCTOBER 2001 REVISED JANUARY 2007 LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO.
TLV320AIC15 Key Features
- Mono 16-Bit Oversampling Sigma-Delta A/D Converter
- Mono 16-Bit Oversampling Sigma-Delta D/A Converter
- Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock
- Selectable FIR/IIR Filter With Bypassing Option
- Max 26 Ksps With On-Chip IIR/FIR Filter
- Max 104 Ksps With IIR/FIR Bypassed
- On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC
- Smart Time Division Multiplexed (SMARTDM™) Serial Port
- Glueless 4-Wire Interface to DSP
- Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses