2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
D Four 12-Bit D/A Converters
D Programmable Settling Time of Either 3 µs
or 9 µs Typ
D TMS320, (Q)SPI, and Microwire
Compatible Serial Interface
D Internal Power-On Reset
D Low Power Consumption:
8 mW, Slow Mode – 5-V Supply
3.6 mW, Slow Mode – 3-V Supply
D Reference Input Buffer
D Voltage Output Range . . . 2 × the Reference
D Monotonic Over Temperature
D Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
D Hardware Power Down (10 nA)
D Software Power Down (10 nA)
D Simultaneous Update
D Battery Powered Test Instruments
D Digital Offset and Gain Adjustment
D Industrial Process Controls
D Machine and Motion Control Devices
D Arbitrary Waveform Generation
D OR PW PACKAGE
The TLV5614 is a quadruple 12-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
LDAC 3 14 OUTA
and Microwire serial ports. The TLV5614 is
DIN 4 13 OUTB
programmed with a 16-bit serial word comprised
SCLK 5 12 OUTC
of a DAC address, individual DAC control bits, and
a 12-bit DAC value. The device has provision for
FS 7 10 REFINCD
two supplies: one digital supply for the serial
interface (via pins DVDD and DGND), and one for
the DACs, reference buffers, and output buffers (via pins AVDD and AGND). Each supply is independent of the
other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the
DAC is controlled via a microprocessor operating on a 3 V supply (also used on pins DVDD and DGND), with
the DACs operating on a 5 V supply. Of course, the digital and analog supplies can be tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage then DACs C and D.
The TLV5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The
TLV5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from
– 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998 – 2003, Texas Instruments Incorporated
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