TMS320C40 Datasheet | Texas Instruments

D Highest Performance Floating-Point Digital Signal Processor (DSP) - ’320C40-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 384M Bytes / s - ’320C40-50: 40-ns Instruction Cycle Time - ’320C40-40: 50-ns Instruction Cycle Time D Six munications Ports D Six-Channel Direct Memory Access (DMA) Coprocessor D Single-Cycle Conversion to and From IEEE-754 Floating-Point Format D Single Cycle, 1/x, 1/Ǹ x D Source-Code patible With TMS320C3x D Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers D Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers D IEEE 1149.1† (JTAG) Boundary Scan patible D Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers: - High Port-Data Rate of 120M Bytes/s (’C40-60) (Each Bus) - 16G-Byte Continuous Program/ Data / Peripheral Address Space - Memory-Access Request for Fast, Intelligent Bus Arbitration - Separate Address-Bus, Data-Bus, and Control-Enable Pins - Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware D 325-Pin Ceramic Grid Array (GF Suffix) D Fabricated Using 0.72-µm Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI™) D Software-munication-Port Reset D NMI With Bus-Grant Feature TMS320C40 DIGITAL SIGNAL PROCESSOR SPRS038 - JANUARY 1996 325-PIN GF GRID ARRAY PACKAGE (BOTTOM...