TMS320C6452
Key Features
- High-Performance Digital Media Processor - 720-MHz, 900-MHz C64x+™ Clock Rates - 1.39 ns (-720), 1.11 ns (-900) Instruction Cycle Time - 5760, 7200 MIPS - Eight 32-Bit C64x+ Instructions/Cycle - Fully Software-Compatible With C64x/Debug - Commercial Temperature Ranges (-720, -900 only) - Industrial Temperature Ranges (-720, -900 only)
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) - 256K-bit (32K-byte) L1P Program RAM/Cache [Direct Mapped] - 256K-bit (32K-byte) L1D Data RAM/Cache [2-Way Set-Associative] - 1408KB L2 Unified Mapped RAM/Cache [Flexible Allocation]
- Supports Little Endian Mode Only
- External Memory Interfaces (EMIFs) - 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O) - Asynchronous 16-Bit Wide EMIF (EMIFA)
- Up to 128M-Byte Total Address Reach
- 64M-Byte Address Reach per CE Space TMS320C64x+™ DSP Core - Glueless Interface to Asynchronous - Eight Highly Independent Functional Units Memories (SRAM, Flash, and EEPROM) With VelociTI.2 Extensions: - Synchronous Memories (SBSRAM and ZBT
- Six ALUs (32-/40-Bit), Each Supports SRAM) Single 32-bit, Dual 16-bit, or Quad 8-bit - Supports Interface to Standard Sync Devices Arithmetic per Clock Cycle and Custom Logic (FPGA, CPLD, ASICs,
- Two Multipliers Support Four 16 x 16-bit etc.) Multiplies (32-bit Results) per Clock Cycle
- Enhanced Direct-Memory-Access (EDMA) or Eight 8 x 8-bit Multiplies (16-Bit Controller (64 Independent Channels) Results) per Clock Cycle
- 3-Port Gigabit Ethernet Switch Subsystem - Load-Store Architecture With Non-Aligned Support
