TMS320C6457
Key Features
- Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times
- Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK
- Corrected PLL2 - Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table
- Removed PLLOUT term from the PLL2 Clock Frequency ranges table
- Fixed typo for the McBSP timing parameters. “P = 1/CORECLK” now correctly reads “P = 1/SYSREFCLK”
- Fixed typo in 7.3.1 Power-Supply Sequencing
- The SPRAAG5 reference now correctly references SPRAAV7
