TMS320C6670 Datasheet | Texas Instruments

Description /ments Updated PASS PLL section (block diagram, PASS PLL Control Register, and initialization sequence) Updated Switch Fabric Matrix tables with bridge numbers and added Switch Fabric block diagrams Updated the JTAGID register table Restricted Output_Divide of SECCTL to max value of divide by 2 Changed TPTCn to EDMA3TCn and TPCCn to EDMA3CCn throughout the data manual Replaced all INTC with CIC and CPT with Tracer throughout the document Updated main PLL lock time Added DDR3PLL and PASS PLL Reset bits in DDR3PLLCTL1 and PASSPLLCTL1 registers Added the DDR3PLL and PASSPLL Initialization Sequence Added po_vcon_smpserr_intr Smart Reflex event Corrected the SPI and DDR3/Hyperbridge Config Memory Map end address Added DEVSPEED Register section Removed Parameter Information section from chapter 7 as the content was not relevant Added more description to Boot Sequence section Changed all footnote references from CORECLK to SYSCLK1 Corrected the typo in the address of MACID2 Re-arranged the wording for description of SYSCLK1 Removed example from footnote Updated footnote on AIF jitter value to 4 ps RMS Revised the INTC1 Events Input table, description for BWADJ field, and power sequencing timing tables and diagrams Removed all mentions of HHV and the Max parameters for PHY Sync and Radio Sync Pulses Updated the GMacs and GFlops for 1.2 GHz and changed output skew time for the trace from 500 ps to 1ns Added thermal values to the thermal resistance characteristics table, and Power Supply to Peripheral I/O Mapping table Added register and field description table for DDR3PLLCTL1, PASSPLLCTL1, and Ser Des status and config registers Corrected RESET electrical timing parameters Updated all PLL block Diagrams - Main PLL, DDR PLL, and PASS PLL pleted all tables in Device Operating Conditions chapter Updated/Added Master and Priv ID tables, added Master ID Settings table Added MMR space Updated the power-up sequencing section. RESETFULL must always de-assert after POR...