TMS320C6712D
Key Features
- Hardware Support for IEEE Single-Precision and Double-Precision Instructions
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
- Boot Mode: 8- and 16-Bit ROM Boot -- Little Endian, Big Endian
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- 256M-Byte Total Addressable External Memory Space
- 0.13-m/6-Level Copper Metal Process
- POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
