TMS320C6712D
Key Features
- Hardware Support for IEEE Single-Precision and Double-Precision Instructions
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) D Device Configuration
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
