TMS320DM8165 Datasheet | Texas Instruments

Overview 1.1 Features - High-Performance Da Vinci Digital Media Processors - ARM® Cortex™-A8 RISC Processor - Up to 1.20 GHz - C674x™ VLIW DSP - Up to 1 GHz - Up to 8000 MIPS and 6000 MFLOPS - Fully Software-patible with C67x+ and C64x+™ - ARM Cortex-A8 Core - ARMv7 Architecture - In-Order, Dual-Issue, Superscalar Processor Core - NEON™ Multimedia Architecture - Supports Integer and Floating Point (VFPv3IEEE754 pliant) - Jazelle® RCT Execution Environment - ARM Cortex-A8 Memory Architecture - 32-KB Instruction and Data Caches - 256-KB L2 Cache - 64-KB RAM, 48-KB of Boot ROM - TMS320C674x Floating-Point VLIW DSP - 64 General-Purpose Registers (32-Bit) - Six ALU (32-Bit and 40-Bit) Functional Units - Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point - Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks - Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle - Two Multiply Functional Units - Mixed-Precision IEEE Floating-Point Multiply Supported up to: - 2 SP x SP → SP Per Clock - 2 SP x SP → DP Every Two Clocks - 2 SP x DP → DP Every Three Clocks - 2 DP x DP → DP Every Four Clocks - Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including plex Multiplies, or Eight 8 x 8Bit Multiplies per Clock Cycle - C674x Two-Level Memory Architecture - 32-KB L1P and L1D RAM and Cache - 256-KB L2 Unified Mapped RAM and Caches - System Memory Management Unit (System MMU) - Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses - 512KB of On-Chip Memory Controller (OCMC)...