TMS320F28021 Datasheet | Texas Instruments

Features - High-efficiency 32-bit CPU (TMS320C28x) - 60 MHz (16.67-ns cycle time) - 50 MHz (20-ns cycle time) - 40 MHz (25-ns cycle time) - 16 × 16 and 32 × 32 MAC operations - 16 × 16 dual MAC - Harvard bus architecture - Atomic operations - Fast interrupt response and processing - Unified memory programming model - Code-efficient (in C/C++ and Assembly) - Endianness: Little endian - Low cost for both device and system: - Single 3.3-V supply - No power sequencing requirement - Integrated power-on and brown-out resets - Small packaging, as low as 38-pin available - Low power - No analog support pins - Clocking: - Two internal zero-pin oscillators - On-chip crystal oscillator and external clock input - Watchdog timer module - Missing clock detection circuitry - Up to 22 individually programmable, multiplexed GPIO pins with input filtering - Peripheral Interrupt Expansion (PIE) block that supports all peripheral interrupts - Three 32-bit CPU timers - Independent 16-bit timer in each Enhanced Pulse Width Modulator (e PWM) - On-chip memory - Flash, SARAM, OTP, Boot ROM available - Code-security module - 128-bit security key and lock - Protects secure memory blocks - Prevents firmware reverse engineering - Serial port peripherals - One Serial munications Interface (SCI) Universal Asynchronous Receiver/Transmitter (UART) module - One Serial Peripheral Interface (SPI) module - One Inter-Integrated-Circuit (I2C) module - Enhanced control...