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TMS320F28031-Q1 - Microcontrollers

Download the TMS320F28031-Q1 datasheet PDF. This datasheet also covers the TMS320F28030 variant, as both devices belong to the same microcontrollers family and are provided as variant models within a single manufacturer datasheet.

General Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; motor control; and sensing and signal

Key Features

  • High-efficiency 32-bit CPU (TMS320C28x).
  • 60MHz (16.67ns cycle time).
  • 16 × 16 and 32 × 32 MAC operations.
  • 16 × 16 dual MAC.
  • Harvard bus architecture.
  • Atomic operations.
  • Fast interrupt response and processing.
  • Unified memory programming model.
  • Code-efficient (in C/C++ and Assembly).
  • Programmable Control Law Accelerator (CLA).
  • 32-bit floating-point math accelerator.
  • Executes code independent.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TMS320F28030-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
TMS320F28031 Real-Time Microcontrollers
TMS320F28030 Real-Time Microcontrollers
TMS320F28030-Q1 Microcontrollers
TMS320F28032 Real-Time Microcontrollers
TMS320F28032-Q1 Microcontrollers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032 TMS320F28032-Q1, TMS320F28033, TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1 TMS320F28035, TMS320F28035-Q1 SPRS584Q – APRIL 2009 – REVISED JANUARY 2024 TMS320F2803x Real-Time Microcontrollers 1 Features • High-efficiency 32-bit CPU (TMS320C28x) – 60MHz (16.67ns cycle time) – 16 × 16 and 32 × 32 MAC operations – 16 × 16 dual MAC – Harvard bus architecture – Atomic operations – Fast interrupt response and processing – Unified memory programming model – Code-efficient (in C/C++ and Assembly) • Programmable Control Law Accelerator (CLA) – 32-bit floating-point math accelerator – Executes code independently of the main CPU • Endianness: Little endian • JTAG boundary scan support – IEEE Standard 1149.