TMS320F2810 Datasheet | Texas Instruments

Features - High-performance static CMOS technology - 150 MHz (6.67-ns cycle time) - Low-power (1.8-V core at 135 MHz, 1.9-V core at 150 MHz, 3.3-V I/O) design - JTAG boundary scan support - IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture - High-performance 32-bit CPU (TMS320C28x) - 16 × 16 and 32 × 32 MAC operations - 16 × 16 dual MAC - Harvard bus architecture - Atomic operations - Fast interrupt response and processing - Unified memory programming model - 4M linear program/data address reach - Code-efficient (in C/C++ and Assembly) - TMS320F24x/LF240x processor source code patible - On-chip memory - Up to 128K × 16 flash (Four 8K × 16 and six 16K × 16 sectors) - 1K × 16 OTP ROM - L0 and L1: 2 blocks of 4K × 16 each Single Access RAM (SARAM) - H0: 1 block of 8K × 16 SARAM - M0 and M1: 2 blocks of 1K × 16 each SARAM - Boot ROM (4K × 16) - With software boot modes - Standard math tables - External interface (F2812) - Over 1M × 16 total memory - Programmable wait states - Programmable read/write strobe timing - Three individual chip selects - Endianness: Little endian - Clock and system control - On-chip oscillator - Watchdog timer module - Three external interrupts - Peripheral Interrupt Expansion (PIE) block that supports 45 peripheral interrupts - Three 32-bit CPU timers - 128-bit security key/lock - Protects flash/OTP and L0/L1 SARAM - Prevents firmware reverse-engineering...