TMS320VC5402 Overview
D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus D 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators D 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation D pare, Select, and Store Unit (CSSU) for the Add/pare Selection...