TMS570LS3137-EP
Description
The TMS570LS3137-EP device is a high-performance microcontroller family for safety systems. The safety architecture includes the following: Dual CPUs in lockstep CPU and memory built-in self-test (BIST) logic ECC on both the flash and the data SRAM Parity on peripheral memories Loopback capability on peripheral I/Os The TMS570LS3137-EP device integrates the ARM Cortex-R4F Floating-Point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz, providing up to 298 DMIPS.
Key Features
- High-Performance Microcontroller for SafetyCritical Applications - Dual CPUs Running in Lockstep - ECC on Flash and RAM interfaces - Built-In Self-Test for CPU and On-chip RAMs - Error Signaling Module with Error Pin - Voltage and Clock Monitoring
- ARM® Cortex™ - R4F 32-Bit RISC CPU - Efficient 1.66 DMIPS/MHz with 8-Stage Pipeline - FPU with Single- and Double-Precision - 12-Region Memory Protection Unit - Open Architecture with Third-Party Support
- Operating Conditions - Up to 180-MHz System Clock - Core Supply Voltage (VCC): 1.2 V Nominal - I/O Supply Voltage (VCCIO): 3.3 V Nominal - ADC Supply Voltage (VCCAD): 3.0 to 5.25 V - IP Modules GBD for -40°C to 125°C Only includes Flash, MibADC timings, nPORRST, N2HET, and FlexRay
- Integrated Memory - 3MB of Program Flash With ECC - 256KB of RAM With ECC - 64KB of Flash With ECC for Emulated EEPROM
- 16-Bit External Memory Interface
- Common Platform Architecture - Consistent Memory Map Across Family - Real-Time Interrupt Timer (RTI) OS Timer - 96-Channel Vectored Interrupt Module (VIM) - 2-Channel Cyclic Redundancy Checker (CRC)
- Direct Memory Access (DMA) Controller - 16 Channels and 32 Control Packets - Parity Protection for Control Packet RAM - DMA Accesses Protected by Dedicated MPU
- Frequency-Modulated Phase-Locked-Loop (FMPLL) with Built-In Slip Detector
- Separate Nonmodulating PLL
- IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components
