SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
N (DIP) PACKAGE
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
I Audio input for right channel.
I Audio input for left channel.
I Gain select least significant bit. TTL logic levels with compliance to AVCC.
I Gain select most significant bit. TTL logic levels with compliance to AVCC.
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
outputs enabled). TTL logic levels with compliance to AVCC.
I/O Bootstrap I/O for left channel.
Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
O Class-D -H-bridge positive output for left channel.
Power ground for left channel H-bridge.
Internally generated voltage supply for bootstrap capacitors.
I/O Bootstrap I/O for right channel.
O Class-D -H-bridge negative output for right channel.
Power ground for right channel H-bridge.
Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
Analog ground for digital/analog cells in core.
Analog Ground for analog cells in core.
Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
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