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TPS40020 Datasheet Preview

TPS40020 Datasheet

Synchronous Buck Controller

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Not Recommended for New Designs
www.ti.com
TPS40020
8
TPS40021
SLUS535D − MARCH 2003 − REVISED JULY 2007
ENHANCED, LOWĆINPUT VOLTAGEĆMODE
SYNCHRONOUS BUCK CONTROLLER
FEATURES
DESCRIPTION
D Operating Input Voltage 2.25 V to 5.5 V
D Output Voltage as Low as 0.7 V
D 1% Internal 0.7 V Reference
D Predictive Gate DriveN-Channel MOSFET
Drivers for Higher Efficiency
D Externally Adjustable Soft-Start and Short
Circuit Current Limit
D Programmable Fixed-Frequency
100 KHz-to-1 MHz Voltage-Mode Control
D Source-Only Current or Source/Sink Current
D Quick Response Output Transient
Comparators with Power Good Indication
Provide Output Status
D 16-Pin PowerPADPackage
APPLICATIONS
D Networking Equipment
D Telecom Equipment
D Base Stations
D Servers
D DSP Power
The TPS4002x family of dc-to-dc controllers are designed
for non-isolated synchronous buck regulators, providing
enhanced operation and design flexability through user
programmability.
The TPS4002x utilizes a proprietary Predictive Gate
Drivetechnology to minimize the diode conduction
losses associated with the high-side and synchronous
rectifier N-channel MOSFET transistions. The integrated
charge pump with boost circuit provides a regulated 5-V
gate drive for both the high side and synchronous rectifier
N-channel MOSFETs. The use of the Predictive Gate
Drivetechnology and charge pump/boost circuits
combine to provide a highly efficient, smaller and less
expensive converter.
Design flexibility is provided through user programmability
of such functions as: operating frequency, short circuit
current detection thresholds, soft-start ramp time, and
external synchronization frequency. The operating
frequency is programmable using a single resistor over a
frequency range of 100 kHz to 1 MHz. Higher operating
frequencies yield smaller component values for a given
converter power level as well as faster loop closure.
VDD 2.25 V − 5.5 V
TPS40020
1
ILIM/
SYNC
BOOT1 16
VDD
VOUT
VOUT
2 VDD HDRV 15
3 OSNS
SW 14
4 FB BOOT2 13
5 COMP PVDD 12
6 SS/SD LDRV 11
7 RT
PGND 10
8 SGND PWRGD 9
UDG−02094
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPADand Predictive Gate Driveare trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated




etcTI

TPS40020 Datasheet Preview

TPS40020 Datasheet

Synchronous Buck Controller

No Preview Available !

TPS40020
TPS40021
Not Recommended for New Designs
SLUS535D − MARCH 2003 − REVISED JULY 2007
DESCRIPTION (CONTINUED)
www.ti.com
The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit
detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current
function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault
counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for
a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output
every seventh (7th) soft-start cycle.
In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled
ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety
of output L-C component values.
The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The
output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate
drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output
undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either
case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood
output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing.
The transient comparators can be disabled by simply tying the OSNS pin to VDD.
The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This
allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.
INTERNAL BLOCK DIAGRAM
VDD 2
OSNS 3
VDD
0.719 V
PWRGD 9
0.659 V
FB 4
0.69 V +
+
COMP 5
UVLO
OSC
RT 7
IRT
SS
ACTIVE
PWM
CLK
UVLO
PREDICTIVE
GATE
DRIVE(tm)
PWM
LOGIC
FAULT
VDD
CHARGE
PUMP
DRV
PVDD
DRV
ISS
SS/SD 6
SGND 8
SOFT
START
UVLO
CLK
SS
ACTIVE
DCHG
FAULT
COUNTER
VDD
0.28 V
CURRENT LIMIT
COMPARATOR
OC
+
SD
SYNC
UVLO
UVLO
VDD
IRT
1V
13 BOOT2
12 PVDD
16 BOOT1
15 HDRV
14 SW
11 LDRV
10 PGND
1 ILIM/SYNC
DISABLE
+
1.4 V
VDD
UDG−02092
2


Part Number TPS40020
Description Synchronous Buck Controller
Maker etcTI
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TPS40020 Datasheet PDF






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